Modern interfaces for Integrated Circuit (IC) packages, chips, and other devices have ever-increasing terminal densities. Many modern IC devices have so many terminals so tightly clustered that it becomes difficult to construct mutually-segregated conductors to connect carrier lines to each terminal. Signal-carrying terminals and lines are particularly burdensome, since they must be segregated from each other as well as from power and ground lines. Signal lines on an IC device or carrier must have sufficient electrical isolation from other conductors that undesired coupling and leakage paths are avoided.
Terminals in a pattern are principally described by their locations (i.e., of the center point) and their shape (typically square or roundish, and ring-shaped for metal-lined through holes). Each may be coupled to other terminals in the same plane (e.g., a via coupled to a pad). Depending on the structure of circuitry connecting to a set of terminals off-plane, terminals may be categorized as no-connects, power terminals, ground terminals, and signal terminals for connecting to signal lines. The terminal configuration of a pattern is typically repeated in two or more parallel layers, each terminal in each layer coupling to a corresponding terminal on the parallel layer(s).
In this document, an xe2x80x9cinterfacexe2x80x9d is a configuration of conductors and dielectrics arranged to provide electrical coupling to an IC device. An interface generally comprises an inward routing (toward the device) and an outward routing (away from the device) in directions parallel to a reference plane. Most typically, routing on an IC device and the carrier on which it is mounted have a significant cost and technology differential. For this reason, routability of an interface in one direction (i.e., inward or outward) has a much larger cost impact on the system than routability in the other. Despite this, few interface designs to date depart from fully dense terminal grids with uniform circumferential spacing. These interfaces do not dislocate terminals but provide routability in less desirable ways such as adding layers.
A xe2x80x9cpatternxe2x80x9d of terminals most commonly comprises substantially all terminals on a surface of one given type, so terms like xe2x80x9cvia patternxe2x80x9d and xe2x80x9cbond pad patternxe2x80x9d are customary. xe2x80x9cRoutabilityxe2x80x9d of a pattern or inter-terminal zone refers to the context-dependent technical possibility of positioning routing lines so that all signals may escape (inward or outward) from a given pattern. The context of the routing comprises the number of routing layers, the routing line widths and clearances, the terminal sizes and required clearances, the shielding scheme, protections against ground bounce, and other design constraints known in the art.
Commonly used interface schemes for IC packages include Pin Grid Array (PGA), Ball Grid Array (BGA), and Land Grid Array (LGA). PGA packages have an array of pins that are inserted into through-hole pads in a Printed Circuit Board (PCB). BGA packages have an array of pads and are mounted by soldering these pads on the package directly to surface pads on the mount side of the PCB. LGA packages have an array of metal stubs and are mounted to the PCB in a clamp with a compressible interposer material placed between the package and the PCB. For PGA, BGA, and LGA packages the patterns of pads on the PCB (and in the case of LGAxe2x80x94the conductive pattern in the interposer) match the pattern of the pins or pads on the package. These package types can usually interface with a socket also, such as for testing.
IC dies typically connect to the substrate within the IC package using either wire bond or Flip-Chip technology. Flip-Chip is used for high pin count IC dies. The xe2x80x9cpinsxe2x80x9d on a Flip-Chip die are called bump pads. As with the package array technologies, there is a matching pattern of pads on the package substrate. Interconnect on the package substrate is typically used to connect the pads on the substrate (connected directly to the IC die) to the pins, pads, or stubs on the surface of the package that gets inserted, soldered, or pressed to the PCB.
Most PGA, BGA, and LGA arrays use a square or staggered xe2x80x9cgriddedxe2x80x9d terminal pattern. As the number of pins in IC""s increase and with the need to keep these packages small, the spacing between package pins can be as small as 0.5 mm. Since these arrays can have as many as 60 pins on each side and because PCB design rules have minimum trace widths and clearances of 3-4 mils, typically, many PCB signal layers are required to be able to interconnect to the pins of the package. Line, terminal, and dielectric width rules exemplify conventional Design Rules used in the art to confirm a design""s quality before construction. PCB designers assure compliance with Design Rules with software tools called Design Rules Checkers (DRC""s). See U.S. Pat. Nos. 5,634,093 and 4,768,154. In FIG. 1 of the former patent, Design Rule File 2c has rules for clearances between various object pairings, and conformity of a given layout is confirmed by Wiring Pattern Checking Unit 5. In fact, DRC""s can readily confirm that a given pattern complies with any requirement, criterion, or preference stated with sufficient particularity. This simplifies the pattern designer""s task to a mere repositioning of terminals that cause a violation of a Design Rule.
To enable routing in highly dense IC packages, micro-via, blind via, buried via, staggered via, and other technologies have become more common. Similarly, additional layers in IC package substrates are required for interconnections to flip-chip dies. Technologies such as these substantially increase the cost of carrier manufacture, compromising product yields, performance, and reliability. The present invention allows the design of interfaces for high pin count IC devices such that the interface footprints can be small (typically allowing smaller packages), that the carrier can be designed with fewer layers, that more stringent design rules can be satisfied, and that the use of expensive manufacturing processes can be minimized.
The present invention comprises a pattern for an improved interface with routable coupling to substantially all of the signal lines on one xe2x80x9csurfacexe2x80x9d of an IC device. A xe2x80x9csurfacexe2x80x9d of the present invention is typically planar, and typically has a convex outer perimeter. It may also have a convex inner perimeter defining its center. xe2x80x9cSubstantially allxe2x80x9d signals, terminals, or lines may exclude at most about 1-10% of the named set, such as anomalous groups of signal-carrying terminals near a corner or similar groupings. The inventive interface comprises a multiplicity of terminals each coupled to one of the IC device""s signal lines.
Terminals are arranged into patterns, each pattern comprising substantially all terminals of a given xe2x80x9ctypexe2x80x9d within the pattern""s areaxe2x80x94i.e., that are arranged for routing lines off of the plane in a first direction. A selected area of a horizontal PCB may, for example, have a pattern of bond pads arranged for routing lines upward intermingled with a pattern of vias for routing lines downward. An intermediate dielectric layer of a ceramic package has a pattern of vias for routing lines both upward and downward from some reference plane. Terminal patterns as described herein can be employed for patterning of vias, micro-vias, pins, bump pads, bond pads, ball pads and like connectors employed in IC chips, IC package layers and PCB layers.
The present invention partitions the terminals of a pattern into mutually exclusive groups distributed about the center of the pattern. In the common usage of carrier manufacturing (including, but not limited to, that of PCB""s, sockets, multi-chip modules, or plastic IC packages), the xe2x80x9ccenterxe2x80x9d of a pattern may be either a region with few signal terminals or a center point. For typical designs, the center of the pattern is near the center axis of the device. For simplicity, it is preferable that a terminal group be xe2x80x9ccontiguous,xe2x80x9d i.e. contained within a single polygon of fewer than 10-20 sides that excludes terminals of other groups.
Each of the groups of the present invention comprises a plurality of terminals clustered along a xe2x80x9creference segment.xe2x80x9d The reference segments have no physical manifestations per se, but are constructs for arrangements of terminal groups. Several constraints limit the shape and position of the segments. They are generally curvilinearxe2x80x94i.e., arcuate, linear, zigzag, wavy, or having similar shape characteristics and zero width. They can optionally coincide with a segment of directly outward rayxe2x80x94i.e., one that extends directly outward from the center axis or region to the pattern perimeter. As the segments extend outward, they do not double back. That is, each has a rotational position about the center that is a function of the offset distance from the centerxe2x80x94i.e., each extends xe2x80x9cgenerally outward.xe2x80x9d The segments extend continuously from the center of the terminal pattern to the (outer) perimeter of the pattern. They do not cross or overlap the center or one another. Each segment desirably projects within about 30-60 degrees of a ray directly outward from the nearest part of the center.
Reference segments intersect the outer perimeter of the pattern in an annular series of points progressing around the perimeter. Reference segments each extend continuously from the center and do not overlap, and are thus distributed in a successive sequence about the center. A xe2x80x9csuccessive pairxe2x80x9d of reference segments is any reference segment with either a clockwise or counterclockwise neighboring segment. A xe2x80x9csuccessive pairxe2x80x9d of groups (comprising a first group and a second group) also describes those associated with a successive pair of reference segments. K (an integer) segments or groups are circuitously distributed about the center. The number of successive pairs likewise successively distributed about the center will be K (rather than Kxe2x88x921). The two elements of a xe2x80x9csuccessive pairxe2x80x9d are sometimes distinguished from one another as a xe2x80x9cleftxe2x80x9d and a xe2x80x9crightxe2x80x9d for convenience.
In contrast to the broad term xe2x80x9cclustered along,xe2x80x9d the terms xe2x80x9caligned along,xe2x80x9d xe2x80x9ccollinear,xe2x80x9d and xe2x80x9cpositioned onxe2x80x9d are used narrowly in this document to describe exact alignment (i.e., centered on with a zero offset). Terminals in a group need not be positioned on the group""s reference segmentxe2x80x94i.e., they are optionally staggered near it or touching it but not centered on it. Almost all (at least about 90%) of the terminals in each group are each closer to the group""s reference segment than to any of the other reference segments. In a preferred pattern, at least about 50-95% of the terminals in a group are each closer to at least one terminal in the group than to any terminal in another group. For higher terminal density, terminal staggering and non-radial alignment are desirable within each group. Preferably, fewer than about 50-95% of the groups each consist of collinear terminals aligned along a radial ray. Alternatively, at least about 5-50% of the K groups are preferably arranged so that less than half of the group""s terminals are on any one ray extending directly outward from the center. More preferably, less than about 10-25% of a group""s terminals are on any one ray extending directly outward from the center.
xe2x80x9cRoutability zonesxe2x80x9d described herein are non-overlapping, one-piece channels each extending continuously from the center to the perimeter of a pattern, each situated between a successive pair of terminal groups of a pattern, and meeting width and configuration specifications as defined and claimed herein. The routability zones are successively distributed about the center, each having a left boundary (or xe2x80x9csidexe2x80x9d) tangent to the left group and a right boundary tangent to a right group. A routability zone is preferably at least about 2-200 times wider than the pattern""s median inter-terminal spacing (the median distance between each terminal and its nearest neighbor, across all of the terminals of the pattern) over at least about 20-60% of its length. For simplicity, it is preferred that a zone does not overlap the pattern""s reference segments.
The number of qualifying routability zones described herein will be labeled xe2x80x9cL,xe2x80x9d an integer. In a number of routing layers parallel to the reference plane, each routability zone pools spatial resources for more efficient routing. Routability zones are preferably dispersed and numerous: If a pattern comprises K groups, the present invention comprises at least about 0.5K to 0.99 K such routability zones distributed about the center. Because of the foregoing constraints, only one zone between each successive pair of terminal groups can count as a routability zone. Thus, Kxe2x89xa7L.
xe2x80x9cSignal-carryingxe2x80x9d customarily refers to lines and terminals positioned or programmed so that they can readily be used to carry information or to trigger events during device operation. In a preferred pattern, each routability zone is bounded by (i.e., adjacent to) a plurality of signal-carrying terminals belonging to a first group, each closer to a next-innermost or next-outermost terminal in the group than to any terminal in another group of the pattern. The plurality preferably comprises at least 3-20 terminals. It is preferred that the plurality of terminals be xe2x80x9cconsecutive.xe2x80x9d A terminal is xe2x80x9cconsecutivexe2x80x9d with another terminal if no terminal in the pattern intersects the line segment between their centers. A set of three or more terminals are xe2x80x9cconsecutivexe2x80x9d (i.e., in a substantially contiguous grouping) only if each of them is consecutive with another of them. A group of terminals xe2x80x9cboundsxe2x80x9d a zone if any terminal in the group is adjacent to the zone.
Some families of zone shapes facilitate routability more than others. For optimizing outward escape routes of an interface design, it is desirable that at least half of the routability zones are generally wedge-shaped in an outward directionxe2x80x94i.e., constructed so that the widest portion of each zone is adjacent to a point on the outermost third of each neighboring group. A similar outwardly-opening result is obtained if the width of at least half of the routability zones increases substantially monotonically as a function of distance from the center. More preferably, at least about 75-95% of the zones meet one of these criteria. Inward escape routes are similarly optimized by reducing the offset of the innermost third (i.e., lowest ranking) of the terminals in a group so that they have a lower average segment offset magnitude than the other terminals in the group, and a greater dispersion in the outward or radial direction.